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Altera_Forum's avatar
Altera_Forum
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8 years ago

Dynamic phase reconfiguration of ALTPLL in Cyclone IV

I am trying to dynamically control the phase of a clock signal by using an ALTPLL.

Generated a the ALTPLL with phase control signals, but I have not been able to find a detailed description of the signals, timing diagrams or design examples. The ALTPLL IP Core User Guide does not contain much.

Signals that I need more information on are:

Input [2:0] phasecounterselect

Input phaseupdown

Input phasestep

Input scanclk

Output locked

Output phasedone

Does anybody have more information on this.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Thanks, exactly what I was looking for.

    --- Quote End ---

    I have generated an ALT PLL with phase control. When simulating I discovered that the phasedone signal does not behave as stated in Cyclone IV handbook. According to the handbook; the phasedone signal goes inactive (low) for one clock cycle of scanclk when changing phase. Simulations show that phasedone only goes inactive(low) for half a clock cycle of scanclk. I imagine that the simulation shows the behaviour of a model of the PLL hardware block in the FPGA, which leaves me with the question: Do I believe the simulation or the handbook?
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Simulations show that phasedone only goes inactive(low) for half a clock cycle of scanclk. I imagine that the simulation shows the behaviour of a model of the PLL hardware block in the FPGA, which leaves me with the question: Do I believe the simulation or the handbook?

    --- Quote End ---

    Expect that phasedone can be processed in a state machine running at scanclk, keeping the handbook timing specification.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    With Cyclone III and IV, I see phase_done one slightly smaller than one scanclk cycle, means the handbook is basically correct.