Dynamic phase reconfiguration of ALTPLL in Cyclone IV

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Simulations show that phasedone only goes inactive(low) for half a clock cycle of scanclk. I imagine that the simulation shows the behaviour of a model of the PLL hardware block in the FPGA, which leaves me with the question: Do I believe the simulation or the handbook?

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Expect that phasedone can be processed in a state machine running at scanclk, keeping the handbook timing specification.