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Honored Contributor
Honored ContributorDynamic phase reconfiguration of ALTPLL in Cyclone IV
I am trying to dynamically control the phase of a clock signal by using an ALTPLL. Generated a the ALTPLL with phase control signals, but I have not been able to find a detailed description of the...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Simulations show that phasedone only goes inactive(low) for half a clock cycle of scanclk. I imagine that the simulation shows the behaviour of a model of the PLL hardware block in the FPGA, which leaves me with the question: Do I believe the simulation or the handbook? --- Quote End --- Expect that phasedone can be processed in a state machine running at scanclk, keeping the handbook timing specification.
