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Thanks, exactly what I was looking for.
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I have generated an ALT PLL with phase control. When simulating I discovered that the phasedone signal does not behave as stated in Cyclone IV handbook. According to the handbook; the phasedone signal goes inactive (low) for one clock cycle of scanclk when changing phase. Simulations show that phasedone only goes inactive(low) for half a clock cycle of scanclk. I imagine that the simulation shows the behaviour of a model of the PLL hardware block in the FPGA, which leaves me with the question: Do I believe the simulation or the handbook?
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