DSP Builder FIFO

Hi K**bleep**ij Goel

Thanks for your response.
I know that HDL Coder generates HDL code from MATLAB functions, Simulink models (https://www.mathworks.com/help/hdlcoder/getting-started-with-hdl-coder.html).

I was wondering if there is a function that converts HDL code (VHDL or Verilog) into a Simulink block or something similar, as I have Verilog code from a dual clock FIFO memory that I would like to include in a Simulink model.

Regards,

Hi,

Thanks for the recommendation. This is useful for me.
I have implemented some Verilog examples and imported them with the HDL Import function and they worked.
On the other hand, I have implemented a Verilog example of a dual clock FIFO memory and tried to import it, but it gives me error:

Is there anyway to use two clocks in general in DSP? DSP builder does not provide any provision for clock to any of its components. It takes the default clock which one sets in the control block.

Thank you,

Finees

Hi,

Regarding of your last comment I'm a bit confused: "Yes, that will work as a system clock (Maximum Clock). the write clock and read clock will be your normal 1-bit signals and the inputs to it is like clocks, you want to give."

Are you referring to the write and read clock signals in the FIFO when I tried to import from Verilog to the simulation block?

Thanks,

Finees