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Finees's avatar
Finees
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2 years ago
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DSP Builder FIFO

Hi Intel team, I am supporting a customer on a DSP Builder project on MatLab R2022a. However, we need a FIFO block that works with two clocks, one for reading and one for writing, i.e. a dual clock ...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


Currently, we don't have the Dual Clock FIFO in the DSP builder block.


Thank you,

Kshitij Goel


  • Finees's avatar
    Finees
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi K**bleep**ij Goel

    Thanks for your response.
    I know that HDL Coder generates HDL code from MATLAB functions, Simulink models (https://www.mathworks.com/help/hdlcoder/getting-started-with-hdl-coder.html).

    I was wondering if there is a function that converts HDL code (VHDL or Verilog) into a Simulink block or something similar, as I have Verilog code from a dual clock FIFO memory that I would like to include in a Simulink model.

    Regards,