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Finees's avatar
Finees
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2 years ago
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DSP Builder FIFO

Hi Intel team, I am supporting a customer on a DSP Builder project on MatLab R2022a. However, we need a FIFO block that works with two clocks, one for reading and one for writing, i.e. a dual clock ...
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Finees's avatar
Finees
Icon for New Contributor rankNew Contributor
2 years ago

Hi,


Thanks for the recommendation. This is useful for me.
I have implemented some Verilog examples and imported them with the HDL Import function and they worked.
On the other hand, I have implemented a Verilog example of a dual clock FIFO memory and tried to import it, but it gives me error:

Is there anyway to use two clocks in general in DSP? DSP builder does not provide any provision for clock to any of its components. It takes the default clock which one sets in the control block.

Thank you,

Finees