Forum Discussion
Finees
New Contributor
New ContributorDSP Builder FIFO
Hi Intel team, I am supporting a customer on a DSP Builder project on MatLab R2022a. However, we need a FIFO block that works with two clocks, one for reading and one for writing, i.e. a dual clock ...
Hi,
Yes, you can import the HDL. Please use the 16.2.1. HDL Import (intel.com).
It will solve your problem.
Thank you,
Kshitij Goel
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
Currently, we don't have the Dual Clock FIFO in the DSP builder block.
Thank you,
Kshitij Goel
FineesNew Contributor
New ContributorHi K**bleep**ij Goel
Thanks for your response.
I know that HDL Coder generates HDL code from MATLAB functions, Simulink models (https://www.mathworks.com/help/hdlcoder/getting-started-with-hdl-coder.html).
I was wondering if there is a function that converts HDL code (VHDL or Verilog) into a Simulink block or something similar, as I have Verilog code from a dual clock FIFO memory that I would like to include in a Simulink model.
Regards,
