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Finees's avatar
Finees
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2 years ago
Solved

DSP Builder FIFO

Hi Intel team, I am supporting a customer on a DSP Builder project on MatLab R2022a. However, we need a FIFO block that works with two clocks, one for reading and one for writing, i.e. a dual clock ...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


Yes, that will work as a system clock (Maximum Clock). the write clock and read clock will be your normal 1-bit signals and the inputs to it is like clocks, you want to give.


You can share your example design. I will take a look and check how it can be done as per your requirements.

Hope this helps.


Thank you,

Kshitij Goel


  • Finees's avatar
    Finees
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi,

    Regarding of your last comment I'm a bit confused: "Yes, that will work as a system clock (Maximum Clock). the write clock and read clock will be your normal 1-bit signals and the inputs to it is like clocks, you want to give."

    Are you referring to the write and read clock signals in the FIFO when I tried to import from Verilog to the simulation block?

    Thanks,

    Finees