Delay in SPI-to-Avalon-MM IP Response After MAX10 Reset

Hello everyone,

I’m using the SPI-to-Avalon-MM IP to enable communication between an external microcontroller (MSP430) and a MAX10 FPGA (MAX10M50DAF256CG). In my setup, the microcontroller acts as the SPI master, and the FPGA is the slave.

The microcontroller also controls a GPIO line connected to a load switch, allowing it to power the MAX10 on or off. The FPGA receives a 26 MHz external oscillator input, which feeds into a PLL. The PLL’s lock signal is used to generate a system reset.

Here’s the behavior I’m observing: even after the PLL lock signal asserts and the system leaves reset (measured by routing the lock signal to an external FPGA pin and timing from the moment CONF_DONE goes high), it still takes around 9 ms before the FPGA and the SPI-to-Avalon-MM IP start responding to SPI messages from the microcontroller.

My questions are:

• What could be causing this post-reset delay?

• Is there a defined startup time for the FPGA and IP to begin responding?

• I haven’t found documentation on this—are there any relevant resources?

Thanks in advance for your help.