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chrisssynco's avatar
chrisssynco
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4 months ago
Solved

Delay in SPI-to-Avalon-MM IP Response After MAX10 Reset

Hello everyone, I’m using the SPI-to-Avalon-MM IP to enable communication between an external microcontroller (MSP430) and a MAX10 FPGA (MAX10M50DAF256CG). In my setup, the microcontroller acts as t...
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  • ShengN_altera's avatar
    ShengN_altera
    4 months ago

    Hi,


    Let me know if you have any further update or concern?


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 months ago

Hi,


That duration after CONF_DONE signal rising is for device initializing (Initializes internal logic and registers && Enables I/O buffers) before enter user mode if check this document https://cdrdv2-public.intel.com/666495/ug-683865-666495.pdf page 30,32:

The initialization sequence begins after the CONF_DONE pin goes high. The initialization clock source is from the internal oscillator and the MAX 10 device receives enough clock cycles for proper initialization.


Thanks,

regards,

Sheng


  • chrisssynco's avatar
    chrisssynco
    Icon for New Contributor rankNew Contributor
    4 months ago

    The time it takes for the PLL to lock is quick - a consistent 248 us. But shouldn't it be the case that the device should be good to go after the lock signal going high? The device takes much longer to function after this lock signal going high - on the order of milliseconds.