Forum Discussion

chrisssynco's avatar
chrisssynco
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Delay in SPI-to-Avalon-MM IP Response After MAX10 Reset

Hello everyone, I’m using the SPI-to-Avalon-MM IP to enable communication between an external microcontroller (MSP430) and a MAX10 FPGA (MAX10M50DAF256CG). In my setup, the microcontroller acts as t...
Video
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    Let me know if you have any further update or concern?


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Another thing is that could you confirm that the 9ms delay measure not include the internal configuration time? Because internal configuration time will possible take until 9ms if check this document https://cdrdv2-public.intel.com/666495/ug-683865-666495.pdf table 7. Internal configuration time is from nSTATUS goes high to CONF_DONE goes high.


Thanks,

Regards,

Sheng