Hi, I am trying to drive two DDR devices from one instance. I have made the settings in the wizard, so I am getting two clock pairs, 2 cke's and so on. But the ras/cas/adress signals needs to be directly mapped to an io port. My problem is that the DDR devices are connected as standalone units, so i need to "split" the signals. I am doing this by mapping the adress signal to a internal signal, and then mapping the internal signal to the IO ports. (If I drive a single IO it works OK). I am getting this error: Error: WYSIWYG I/O primitive "DDR:DDR_upper_banks|DDR_controller_phy:DDR_controller_phy_inst|DDR_phy:alt_mem_phy_inst|DDR_phy_alt_mem_phy_sii:DDR_phy_alt_mem_phy_sii_inst|DDR_phy_alt_mem_phy_addr_cmd_sii:adc_2t_en_gen.adc|DDR_phy_alt_mem_phy_ac_sii:addr[12].addr_struct|altddio_out:full_rate.addr_pin|ddio_out_7ed:auto_generated|dataout[0]" is not properly connected to a top level pin. Anybody know how I may hack myself around this? Thanks Geir

The DDR core probably maps to IO primitives, which connect directly to their associated IO. So you can't split it and have it drive two. Since you don't actually want two controllers, just a single one that drives a wider bus, you should be able to configure it that way. (Plus, what you're doing would not work from a timing perspective. Having a singel DDR element take the time to drive two pins would throw off the timing quite a bit.)

Hello, the controller IP supports the usual multiple bank structure: sharing all signals except CS and CK. I don't exactly understand, why this technique isn't suitable? Regards, Frank

Hi, yes the PHY maps the command signals directly to IO primitives. The HP controller wizard does not mention no of devices. So I would need to remove the IO primitives and double the command signals output from the PHY for the signals in question: RAS/CAS/ADR//WE/BA. That looks like I will mess up all the scripts. There has to be a smooth way around this. Frank, the HP PHY will not allow you use multiple devices as far as I can see. Where should I look? I am gonna post this with Altera. G

Hello, my understanding is, that multiple devices are configured by parameter memory chip selects in conjunction with chip selects per dimm. The Altmemphy manual (also referred by HP Controller manual regarding memory configuration details) explains the meaning of the said parameter: --- Quote Start --- Memory chip selects 1, 2, 4, or 8 The number of chip selects in your memory interface. This is the depth of your memory in terms of number of chips. --- Quote End --- As an example, when using two 1 GB Mobile SODIMM modules, I would configure Memory chip selects = 4 and Chip selects per DIMM = 2. This implies, that all memory signals except the said chip selects and clock signals would be tied together als usual. Regards, Frank

Hi, true but it will still assume that all command signals are tied together OUTSIDE the chip. The devices in this design are all total independent. I will try to generate to separate instances ,one master and one slave (AN 462), an see if they can be operated sync'd.

DDR/DDR2 HP compiler - multiple devices

12 Replies

Altera_Forum
Honored Contributor
17 years ago
The DDR core probably maps to IO primitives, which connect directly to their associated IO. So you can't split it and have it drive two. Since you don't actually want two controllers, just a single one that drives a wider bus, you should be able to configure it that way. (Plus, what you're doing would not work from a timing perspective. Having a singel DDR element take the time to drive two pins would throw off the timing quite a bit.)
Altera_Forum
Honored Contributor
17 years ago
Hello,

the controller IP supports the usual multiple bank structure: sharing all signals except CS and CK. I don't exactly understand, why this technique isn't suitable?

Regards,
Frank
Altera_Forum
Honored Contributor
17 years ago
Hi,
yes the PHY maps the command signals directly to IO primitives.
The HP controller wizard does not mention no of devices.

So I would need to remove the IO primitives and double the command signals output from
the PHY for the signals in question: RAS/CAS/ADR//WE/BA.
That looks like I will mess up all the scripts. There has to be a smooth way around this.

Frank, the HP PHY will not allow you use multiple devices as far as I can see.
Where should I look?

I am gonna post this with Altera.

G
Altera_Forum
Honored Contributor
17 years ago
Hello,

my understanding is, that multiple devices are configured by parameter memory chip selects in conjunction with chip selects per dimm. The Altmemphy manual (also referred by HP Controller manual regarding memory configuration details) explains the meaning of the said parameter:

--- Quote Start ---
Memory chip selects 1, 2, 4, or 8
The number of chip selects in your memory interface. This is the depth of your memory in terms of number of chips.
--- Quote End ---

As an example, when using two 1 GB Mobile SODIMM modules, I would configure Memory chip selects = 4 and Chip selects per DIMM = 2. This implies, that all memory signals except the said chip selects and clock signals would be tied together als usual.

Regards,
Frank
Altera_Forum
Honored Contributor
17 years ago
Hi,
true but it will still assume that all command signals are tied together OUTSIDE the chip.
The devices in this design are all total independent.
I will try to generate to separate instances ,one master and one slave (AN 462), an see if they can be operated sync'd.
Altera_Forum
Honored Contributor
17 years ago
Hello,

unfortunately, I don't yet understand your requirements for the DDR core. Do you want to operate the two chips independently, e. g. read one at an address, write the other at a different address, or combined to a memory array, accessing them mutual exclusive, as usual with multiple memory modules in a computer, or simultaneously, which would mean nothing else but doubling the data width? Or in another way, I can't yet imagine?

Regards,
Frank
Altera_Forum
Honored Contributor
17 years ago
I would like the chips to operate as one. But they are mounted as separete devices on the board. (It's an old design).

The problem is to tell the IP that I need to split the command signals. It will not let you do that. Not without messing inside the controller. Which I do not have time to.

regards

geir
Altera_Forum
Honored Contributor
17 years ago
Hello,

--- Quote Start ---
I would like the chips to operate as one
--- Quote End ---

I understand that you wan't to operate the chips in the way I called simultaneously, e. g. using two 16 bit wide chips as a 32 bit memory? That's of course supported by the controller, cause it's the same as using the chips within a module. You only have to set the respective memory organisation in Megawizard.

Referring to previous example: Using a 1 GByte SODIMM module means having the controller accessing 16 individual 8-bit wide memory chips, organized in two banks of 8 chips each.

Regards,
Frank
Altera_Forum
Honored Contributor
17 years ago
Hi,
well the HP compiler core will NOT let you split the command signals while the legacy compiler will.

You will get the WYSIWYG error. I have to figure out a way to generate an array[2] of command signals and then map them to the ALT_DDIO primitive. Or something like that.

For now it looks like i'm going with the "old way".

"That's of course supported by the controller, cause it's the same as using the chips within a module"
It is not. A module has only one set of command signals.

Regards

Geir
Altera_Forum
Honored Contributor
17 years ago
Hello,

but I don't see why you need to split the command signals when you like the chips to operate as one. What do you want to achieve this way?

Regards,
Frank

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DDR/DDR2 HP compiler - multiple devices

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