Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

DDR2 High Performance Bidirectional I/O Error

Hi

I am using Altera Stratix-III FPGA development board with EP3SL150F1152C2 FPGA. I instantiated DDR high performance IP core in SOPC. Before compilation, I also executed the scripts generated by SOPC (ddr2_ctrl_pin_assignment.tcl and ddr2_ctrl_phy_ddr_pins.tcl). I am using this controller at full-rate at 267 MHz clock rate. Analysis and Synthesis is passed but during Fitting, first I get this warning message:

warning: pin ddr2_dimm_clk[2:1] must use pseudo-differential i/o standard

Then it automatically assigns LVDS_E_3R pseudo-differential I/O standard to ddr2_dimm_clk and ddr2_dimm_clk_n pins (except LSB).

Then Fitter fails giving following error message:

error: differential i/o standard lvds cannot be used on the bidir pin ddr2_dimm_clk[0]

In QSF File, I/O standard on these pins is already set to SSTL-18 Class I.

In .QSF file, these TCL scripts have automatically added constraint TREAT_BIDIR_AS_OUTPUT on ddr2_dimm_clk_n[2:1] and ddr2_dimm_clk[2:1] bidirectional outputs (two MSB's only). I dont know if I should manually add same constraint for ddr2_dimm_clk_n[0] and ddr2_dimm_clk[0]?

I cannot figure out what is the problem and how to get rid of it. Please help.

Regards

Faisal

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I received similar kinds of errors trying to run the DDR2 High Performance Controller on a Terasic DE3 Stratix III Board.

    The doing the following would bring up pseudo-differential errors

    -not setting the use differential dqs or enable dynamic parallel on-chip termination (oct) options for the ddr controller under PHY Settings

    -not running the following 3 scripts:

    <ddr_ctrl_name>_phy_dq_groups.tcl

    <ddr_ctrl_name>_phy_ddr_pins.tcl

    <ddr_ctrl_name>_assignments.tcl

    I hope this helps
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Could setting "differential pair" in pin planner for all "ddr2_dimm_clk" solve such errors ?

    My understanding is that

    ddr2_dimm_clk and ddr2_dimm_clk_n should use differential I/O standard,

    and each ddr2_dimm_clk and ddr2_dimm_clk_n should paired to each other in Pin Planner "differential pair" column.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Could setting "differential pair" in pin planner for all "ddr2_dimm_clk" solve such errors ?

    My understanding is that

    ddr2_dimm_clk and ddr2_dimm_clk_n should use differential I/O standard,

    and each ddr2_dimm_clk and ddr2_dimm_clk_n should paired to each other in Pin Planner "differential pair" column.

    --- Quote End ---

    You would think so, but apparently there is a double constraint. The settings for differential I/O have be set at both the pin side and the DDR2 Controller side.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    You would think so, but apparently there is a double constraint. The settings for differential I/O have be set at both the pin side and the DDR2 Controller side.

    --- Quote End ---

    I actually didn't see such problem on my board...

    Do you mean the error will resolve by setting differential-pair on both the DDR2 controller and the pin planner ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It doesn't surprise me that you're not getting the error. It's a little quirky in that it won't always complain about the same thing sometimes it's a problem with differential I/O or invalid termination statement depending on how you set up your pin settings (.csv file, tcl scripts, or a 3rd party application like DE3_System_Builder). I'm using Quartus II 8.0 so it is also possible that later versions no longer have the problem.

    I just read a different thread on the same problem, but different error (see yossarian's post on dynamic termination control http://www.alteraforum.com/forum/showthread.php?t=2904). I think it seems like there is a redundant constraint because simply setting differential lines in the assignment editor isn't enough. It is also necessary to set up dynamic parallel termination which for whatever reason doesn't always carry over from one project to another through assignment import/export. Setting OCT in the DDR2 controller however puts the necessary commands in the tcl scripts for setting up the pin assignments.