Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

DDR2 High Performance Bidirectional I/O Error

Hi I am using Altera Stratix-III FPGA development board with EP3SL150F1152C2 FPGA. I instantiated DDR high performance IP core in SOPC. Before compilation, I also executed the scripts generated...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

You would think so, but apparently there is a double constraint. The settings for differential I/O have be set at both the pin side and the DDR2 Controller side.

--- Quote End ---

I actually didn't see such problem on my board...

Do you mean the error will resolve by setting differential-pair on both the DDR2 controller and the pin planner ?