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Altera_Forum
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16 years ago

DDR2 High Performance Bidirectional I/O Error

Hi I am using Altera Stratix-III FPGA development board with EP3SL150F1152C2 FPGA. I instantiated DDR high performance IP core in SOPC. Before compilation, I also executed the scripts generated...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I received similar kinds of errors trying to run the DDR2 High Performance Controller on a Terasic DE3 Stratix III Board.

The doing the following would bring up pseudo-differential errors

-not setting the use differential dqs or enable dynamic parallel on-chip termination (oct) options for the ddr controller under PHY Settings

-not running the following 3 scripts:

<ddr_ctrl_name>_phy_dq_groups.tcl

<ddr_ctrl_name>_phy_ddr_pins.tcl

<ddr_ctrl_name>_assignments.tcl

I hope this helps