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Altera_Forum
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17 years ago

DDR2 High Performance Bidirectional I/O Error

Hi I am using Altera Stratix-III FPGA development board with EP3SL150F1152C2 FPGA. I instantiated DDR high performance IP core in SOPC. Before compilation, I also executed the scripts generated...
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Altera_Forum
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17 years ago

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Could setting "differential pair" in pin planner for all "ddr2_dimm_clk" solve such errors ?

My understanding is that

ddr2_dimm_clk and ddr2_dimm_clk_n should use differential I/O standard,

and each ddr2_dimm_clk and ddr2_dimm_clk_n should paired to each other in Pin Planner "differential pair" column.

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You would think so, but apparently there is a double constraint. The settings for differential I/O have be set at both the pin side and the DDR2 Controller side.