Forum Discussion
Altera_Forum
Honored Contributor
17 years agoDDR2 High Performance Bidirectional I/O Error
Hi I am using Altera Stratix-III FPGA development board with EP3SL150F1152C2 FPGA. I instantiated DDR high performance IP core in SOPC. Before compilation, I also executed the scripts generated...
Altera_Forum
Honored Contributor
17 years agoIt doesn't surprise me that you're not getting the error. It's a little quirky in that it won't always complain about the same thing sometimes it's a problem with differential I/O or invalid termination statement depending on how you set up your pin settings (.csv file, tcl scripts, or a 3rd party application like DE3_System_Builder). I'm using Quartus II 8.0 so it is also possible that later versions no longer have the problem.
I just read a different thread on the same problem, but different error (see yossarian's post on dynamic termination control http://www.alteraforum.com/forum/showthread.php?t=2904). I think it seems like there is a redundant constraint because simply setting differential lines in the assignment editor isn't enough. It is also necessary to set up dynamic parallel termination which for whatever reason doesn't always carry over from one project to another through assignment import/export. Setting OCT in the DDR2 controller however puts the necessary commands in the tcl scripts for setting up the pin assignments.