Clocked Video IP for NTSC bt656

thanks for your response.

Yes i do seem to be getting video data out, but not sure if it correct. I know that the the video IC is doing something as it is definitely sending a signal to myscreen.

I was little confused by the question of using 10 bits and 2 symbols or 8 bits and 2 symbols.

not sure what the 10 bits , standard altera settings are for?

I am not even sure if my Blanking setting are right.

regards nadeem

Sorry I am not familiar with the IP cores you are using but this article on inserting BT656 TRS codes may help, http://www.singmai.com/sdi.htm.

If you are getting a green screen then that normally indicates the Y and C are swapped.

Nadeem

I failed at several attempts to get the Test Pattern Generator to send data to the Clocked Video Output and then on to a Video Encoder in BT-656 format using VIP. I tried inside SOPC Builder and Inside Qsys. Both failed and I thought it was the tools. I finally moved both the TPG and CVI blocks to a the Quartus II block level (BSF). The setup attached displays color bars running on a normal NTSC monitor. I attached a PDF file showing the steps I used and hope it is helpful to you, or someone else, that has a similar problem. Seeing Color Bars on an NTSC monitor was my only goal in this write up. It requires I2C inititialization via NIOS2 for the ADI color encoder and a 27MHZ clock.

In your text you mention entering a variety of field lenghts for F0 and F1 fields. I tried to do this and the vertical sync was being written over by the CrYCbY data until (using the 100th monkey algorithm) I got this version (see attached PDF) to produce color bars. In the latest version of VIP there is an NTSC setup button that sets most of the parameters correctly.

There may be better ways to do this but at least this is one way to see that the hardware works. I am a new-user and am in awe of the people that have done this type of work for many years. They make it look simple. It is "after it works". Till then it is not simple at all.

Lyle

The other thing you may want to look at in the data sheet is the i2c MPU port.

You may need to set some registers inside the chip appropriately in order to have it generate video correctly.

Also, it looks like you may be able to have the chip generate a color test pattern internally and output it to your monitor.

You may want to try and get this feature to work before sending it video from your FPGA.

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I finally moved both the TPG and CVI blocks to a the Quartus II block level (BSF).

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In the latest version of VIP there is an NTSC setup button that sets most of the parameters correctly.

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Hello, lrp!

Which of two above acts really helped?

Hello, lrp !

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In the latest version of VIP there is an NTSC setup button that sets most of the parameters correctly.

Lyle

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Do You mean, that some NTSC parameters are still set incorrectly by setup button?

What constraints did You use for that project?

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I finally moved both the TPG and CVI blocks to a the Quartus II block level (BSF).

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How did You do that?

Created the connections in QSYS and then generated *.bsf or You did not use QSYS at all?

Aphraton

Your first question is: Which of two above acts really helped? Answer: The settings actually helped. These blocks work equally well inside the QSYS module or outside in block form. The file I attached to Message# 5 above shows them in block form.

Your second question: Do I mean that the NTSC default setting can result in incorrect settings? Yes. The PDF attached in# 5 spells out the sequence of settings and the values I used to get NTSC 720X480 color bars using the Altera IP. You need to send 8 bit data or 10 bit data depending on your encoder. My encoder is set to 8 bits in this example. The tricky value was the number of lines. Changing it even one or two in any direction causes very bad vertical sync problems. (which, in hind-sight, it should)

gwall (message#6) correctly mentions that the first step is to turn color bars on via I2C in the video encoder. They should be perfect on an o-scope or vectorscope or waveform monitor for 75% color bars. The DAC current setting resistor on the ADI part I used needed to be 4.12K with a 300 ohm load going into the 2:1 gain op amp. That LPF needs to move between the output of the encoder and the amp to remove the A/D noise or you can use the ADI app note which indicates a cap/inductor/cap filter in discretes. The I2C address and data to set up the ADI encoder is included in the little PDF I posted. NIOS is only used to set up the OpenCores I2C and send out the initial data.

After you get the color bars to show up correctly you only need to switch some I2C registers to allow the 27MHZ YUV data to drive the encoder at 75%. The two match nearly exactly but not 100%. The Altera generated color bars are 3% lower in luma than the ADI generated data and they have smoother transitions between the color bars.

I use a VTM-3100 vectorscope and took some pictures with my cell phone. I attached images from both cases: 1. ADV7393 internally generated colorbars and 2. ADV7393 generating color bars from the 27MHZ YUV stream from the Altera IP. These two groups of photos show the difference in the colorbars that are internally generated and those that are generated using the Altera IP.

There is also a modified encoder schematic showing the LPF. This does not use the high current output and low impedance matching that ADI recommends but saves a lot of power in the DAC output.

I apologize for not getting back sooner. My email was killing the messages from this forum and I have had a busy time.

LRP

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It requires I2C inititialization via NIOS2 for the ADI color encoder and a 27MHZ clock.

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I studied Your project as a tutorial. It really helped!

Would You please post Your NIOS II + I2C design to show how to program NIOS to do I2C inititialization and how to set I2C bidirectional pins in open collector mode.

Or at least please point me to some good tutorial on this subject.