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Altera_Forum
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17 years ago

Clocked Video IP for NTSC bt656

Hello everyone,

I desperately need help with getting my embedded sync bt656 clocked out IP to work.

I have connected the test generator module found in the VP 8.0 reference example, and connected it to the Clocked Out video ip.

Then connected the Video output 8 bit bus to my ADV7171 video IC.( which has been tested with its internal color bar.)

The test generator is set to send := 422 ycrcb 720 by 486

The Video Clocked out IP is set to Embedded sync mode, 720 by 486 active picture and 8 bit , 2 symbols per beat and interlaced.

synce field one is

Active Picture line=20

Horizontal Blanking =138

Vertical Blanking = 20

Field zero

F rising=266

F falling =4

vertical blanking rising edge line =264

vertical blanking =19

All I end up getting is a black screen, and when brightness is turned up it is light green vertical lines. Please can some one help me with this problem , it will be greatly appreciated.

regards,

Nadeem

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I studied Your project as a tutorial. It really helped!

    Would You please post Your NIOS II + I2C design to show how to program NIOS to do I2C inititialization and how to set I2C bidirectional pins in open collector mode.

    Or please point me to some good tutorial on this subject.

    --- Quote End ---

    Aphraton

    I remember using Quartus version 7.x and editing the pin list to insure that each one correctly corresponded to the needs of the project. Any discrepancy was met with many glaring compiler errors so one quickly learned the ropes. However the newer version of the compiler seems to use the input/output declarations in the Verilog code to assign the pin type. In the attached PDF I put several more screen grabs of that project and some source code for you to look at. Please let me know what parts of this are still not clear.

    lrp
  • Altera_Forum's avatar
    Altera_Forum
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    Thank You, lrp!

    What i2C IP did You use? OpenCores or something else?

    Did You use any custom presest in NIOS II instantiation?

    Is NIOS II /e ( free economical edition ) enough to intialize ICs via I2C?
  • Altera_Forum's avatar
    Altera_Forum
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    Aphraton : Re: Clocked Video IP for NTSC bt656

    What i2C IP did You use? OpenCores or something else? Yes. This project used the OpenCores I2C routines.

    Did You use any custom presest in NIOS II instantiation? No. This is simplest NIOS II/e with internal SRAM.

    Is NIOS II /e ( free economical edition ) enough to intialize ICs via I2C? Yes. I2C and serial I/O are roughly equivalent to PIO in complexity. The NIOS II/e is way overkill for all these functions. Recall that these all can be done easily in any 8 bit processor and the resources needed are very few. I2C is mostly a matter of getting a dual trace scope connected to SCL and SDA. Verify the 100KHZ/400KHZ bit rate, the clock timing/polarity and the start/stop/restart transitions. Keep the initial message SHORT and force the same message to occur 4-10 times per second so you can sync the scope easily. Use one trace for clock and one for data and watch that the ACK bit is being pulled low by the slave. Then change the address and watch that the ACK bit is not being pulled low. At some point you get the first I/O byte to go out and come in. After that you simply change the address and use auto-increment to send multiple bytes. Problems in more complex protocol exchanges can be sussed out with simple analyzers that have built-in protocol analyzers. I use Saleae Logic-16 16 channel USB Logic Analyzer to simplify the process when it gets more complicated than a simple I/O device. For this level of project (Video Encoder/Decoder) you should use printf to the JTAG serial port and watch the system initialize as you expect. The printf statements can be commented out. The basic rule for debug statements is to not delete them, just comment them out because "if you used them once you will use them again". You will use them again, for instance, if you need to change the driver or use a slightly different chip in the future. In general use NIOSII/e with internal memory to get things started when bringing up new hardware. You can trust that a NIOS II/e with internal memory will ALWAYS boot and run regardless if other external memory is working correctly or not. You can get simple drivers running and use it to memory test flash/sram/dram etc. You can trust the FPGA to run correctly if the core is running and JTAG is good. New hardware must be assumed to be bad when you first bring up any board. It takes time but you must verify each line of code and every net on the schematic one-by-one. I have written bit-banged I2C routines and the OpenCores are much better because the processor is not trapped at a bit level. The OpenCore I2C routines are great. lrp
  • Altera_Forum's avatar
    Altera_Forum
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    Hello, lrp!

    I am now beginning to test Your C code for I2C initialization and I before I started have several questions / comments:

    1). In the datasheet "I2C Master core" ( i2c_specs.pdf ) from Opencores prescale is calculated in a different way, than in Your code.

    2). Unsleep function doesn't produce pauses, stated in corresponding comments.

    3). Where from can I get "i2c.h", "links.h" files, that are# include(d) in C code? They are not included in "I2C Master core" from Opencores.

    Maybe should I use "i2c_opencores_regs.h" or "i2c_opencores.h" and "linker.h" instead?

    P.S. I found the solution by myself.