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srilakshmi's avatar
srilakshmi
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2 years ago

clarifications about Sync Header positions getting changed after 128b/130b block in pcie

Hi ,

I am using the below specification document.

PHY Interface for the PCI Express*, SATA, USB 3.2, DisplayPort*, and USB4* Architectures
January 2023

Revision 6.2

we are using serdes architecture for pcie.

Could you please clairfy the following.

with 128b/130b encoding, a block is 130 bits in length., Sync Headers are expected in bits 0 and 1 and the block ends with bit 129. This is the expected alignment for all received blocks.If the Receiver receives an EIEOS where the Sync Header appears in bits 2 and 3 rather than bits 0 and 1, then the Receiver must change its alignment such that the Sync Header appears in bits 0 and 1 once again.

could you please provide the clarifications in which scenario mac will receive Sync Header in bit position 2 and 3 . instead of bit position 0 and 1.

Pcie

5 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @srilakshmi,


    Thanks for reaching out to Intel Community Forum.


    As you're using the SerDes Architecture for PCIe, the RxSyncHeader[3:0] is not used in the SerDes Architecture. Instead, it is used in the original PIPE only.


    Thanks.

    Best Regards,

    VenTing_Intel


    • srilakshmi's avatar
      srilakshmi
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi Ven Ting,

      Thanks for information. could you please let me know whether sync header positions can be changed because of PHY that is whether they can occure in bit positions 1 and 2 rather than in positions 0 and 1 as described above. although they are generated in MAC whether that shifting can happen because of PHY .

      Thanks

      Srilakshmi

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @srilakshmi,


    May I know which FPGA board, PCIe IP, PCIe Gen that you're targeting where you encountered this situation?


    Thanks.

    Best Regards,

    VenTing_Intel


    • srilakshmi's avatar
      srilakshmi
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi VenTingT,

      I have not encountered this issue. but I want to verify it as the scenario is specified in pcie gen6 specification docuement.

      Thanks

      Srilakshmi

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi @srilakshmi,


    We should follow the base specification.


    Currently, the Intel PCIe IP generation provides support until Gen 5. Since this is not a use case for our product, kindly open a new thread when you encounter the situation in the future.


    With that, I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.


    Thanks.

    Best Regards,

    VenTing_Intel