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srilakshmi's avatar
srilakshmi
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2 years ago

clarifications about Sync Header positions getting changed after 128b/130b block in pcie

Hi , I am using the below specification document. PHY Interface for the PCI Express*, SATA, USB 3.2, DisplayPort*, and USB4* Architectures January 2023 Revision 6.2 we are using serdes archit...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @srilakshmi,


May I know which FPGA board, PCIe IP, PCIe Gen that you're targeting where you encountered this situation?


Thanks.

Best Regards,

VenTing_Intel


  • srilakshmi's avatar
    srilakshmi
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    2 years ago

    Hi VenTingT,

    I have not encountered this issue. but I want to verify it as the scenario is specified in pcie gen6 specification docuement.

    Thanks

    Srilakshmi