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srilakshmi's avatar
srilakshmi
Icon for New Contributor rankNew Contributor
2 years ago

clarifications about Sync Header positions getting changed after 128b/130b block in pcie

Hi , I am using the below specification document. PHY Interface for the PCI Express*, SATA, USB 3.2, DisplayPort*, and USB4* Architectures January 2023 Revision 6.2 we are using serdes archit...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @srilakshmi,


We should follow the base specification.


Currently, the Intel PCIe IP generation provides support until Gen 5. Since this is not a use case for our product, kindly open a new thread when you encounter the situation in the future.


With that, I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.


Thanks.

Best Regards,

VenTing_Intel