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srilakshmi's avatar
srilakshmi
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2 years ago

clarifications about Sync Header positions getting changed after 128b/130b block in pcie

Hi , I am using the below specification document. PHY Interface for the PCI Express*, SATA, USB 3.2, DisplayPort*, and USB4* Architectures January 2023 Revision 6.2 we are using serdes archit...
Pcie
VenT_Altera's avatar
VenT_Altera
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2 years ago

Hi @srilakshmi,


Thanks for reaching out to Intel Community Forum.


As you're using the SerDes Architecture for PCIe, the RxSyncHeader[3:0] is not used in the SerDes Architecture. Instead, it is used in the original PIPE only.


Thanks.

Best Regards,

VenTing_Intel


  • srilakshmi's avatar
    srilakshmi
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi Ven Ting,

    Thanks for information. could you please let me know whether sync header positions can be changed because of PHY that is whether they can occure in bit positions 1 and 2 rather than in positions 0 and 1 as described above. although they are generated in MAC whether that shifting can happen because of PHY .

    Thanks

    Srilakshmi