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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
2 months ago
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Clarification on TX/RX P&N Invert feature support in TSE IP core

Hello,

Based on the page below from the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs (version 25.1, “Analog Parameter Options” section), the “Enable TX P&N Invert” and “Enable RX P&N Invert” options are described as preliminary and not supported in hardware:
3.3.11. Analog Parameter Options

However, according to the updated page for version 25.1.1, those same features are now marked as supported in hardware:
3.3.11. Analog Parameter Options

In the Analog Parameters tab of the Triple-Speed Ethernet (TSE) Intel FPGA IP, these TX/RX P&N Invert options also appear as configurable parameters.

Could you please confirm whether these features are expected to function in Quartus Prime Pro 25.1.1 and Quartus Prime Pro 25.3 when used in the TSE IP core?

Also, could you please let us know what happens if we enable these P/N inversion options in Quartus 25.1, since the documentation indicates that they are not supported in hardware in that release?

Thank you in advance for your help and clarification.

Best regards,

Ethernet
Transceiver
  • Sahil_Patni's avatar
    Sahil_Patni
    2 months ago

    Hi,

    Yes,  when you enable the TX/RX P&N Invert options in the TSE IP Analog Parameters GUI, you must also perform the Attribute Access Method steps (as described in GTS Attribute Access Method Example 3) after entering user mode.

    This requirement applies because the TSE IP uses the same underlying PMA attributes as the GTS PHY. The GUI setting alone doesn’t apply the inversion until the attribute access sequence is executed.

    Best Regards,

    Sahil Patni

8 Replies

  • Sahil_Patni's avatar
    Sahil_Patni
    Icon for New Contributor rankNew Contributor
    2 months ago

    Hi,

    Regarding your first point - the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs (version 25.1, “3.3.11. Analog Parameter Options” section) marks the TX/RX P&N Invert options as “Preliminary – pending hardware verification” because these features had not yet been validated on hardware at that time. Starting from Quartus Prime Pro 25.1.1, the features were successfully verified on hardware.

    Q: Are these features expected to function in Quartus Prime Pro 25.1.1 and Quartus Prime Pro 25.3 when used in the TSE IP core?
    A: Yes, these features are supported and functional starting from version 25.1.1 and later, including 25.3.

    Q: What happens if we enable these options in Quartus 25.1, where they were not yet supported in hardware?
    A: While the feature may still compile and appear to work, it was not hardware-verified in 25.1, so we recommend using 25.1.1 or later for reliable operation.

    Best regards,
    Sahil Patni

    • fa_fpga_enthusiast's avatar
      fa_fpga_enthusiast
      Icon for Occasional Contributor rankOccasional Contributor
      2 months ago

      Hello,

      Thank you for your detailed reply.

      Based on the following documentation:
      3.3.11. Analog Parameter Options

      When using the Analog Parameter GUI options to invert the PMA P and N pin polarity, it mentions that after entering user mode, the Attribute Access Method steps (as described in the “GTS Attribute Access Method Example 3” section) must be executed.

      Could you please clarify if the same requirement applies when the TX/RX P&N invert options are enabled through the Analog Parameters in the TSE IP core?
      In other words, is enabling these options in the GUI sufficient for the TSE IP core, or do we also need to perform additional steps similar to those required for the GTS?

      Best regards,

      • Sahil_Patni's avatar
        Sahil_Patni
        Icon for New Contributor rankNew Contributor
        2 months ago

        Hi,

        Yes,  when you enable the TX/RX P&N Invert options in the TSE IP Analog Parameters GUI, you must also perform the Attribute Access Method steps (as described in GTS Attribute Access Method Example 3) after entering user mode.

        This requirement applies because the TSE IP uses the same underlying PMA attributes as the GTS PHY. The GUI setting alone doesn’t apply the inversion until the attribute access sequence is executed.

        Best Regards,

        Sahil Patni

  • Anonymous's avatar
    Anonymous
    2 months ago

    Hi,

    Regarding your question about the TSE IP, please allow me some time to further engage with our TSE IP specialist to provide further assistance.

    Thank you.

  • Anonymous's avatar
    Anonymous
    2 months ago

    Hi,

    Thank you for your inquiry regarding the GTS TX and RX polarity inversion features.

    Starting from Quartus version 25.1.1, these features are supported in hardware. However, please note that after enabling the polarity inversion options in the IP GUI, you must also follow the steps outlined in Example 3 of the GTS Attribute Access Method section in the user guide to complete the configuration.

    Regarding your question about the polarity inversion option in Quartus 25.1, since the user guide indicates that it is not supported in hardware, it is likely intended for simulation purposes only.

    Please feel free to reach out if you have any further questions or concerns. Thank you.

  • Anonymous's avatar
    Anonymous
    2 months ago

    Hi,

    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible