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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
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10 months ago
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Clarification on TX/RX P&N Invert feature support in TSE IP core

Hello, Based on the page below from the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs (version 25.1, “Analog Parameter Options” section), the “Enable TX P&N Invert” and “Enable RX P&N Inv...
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Transceiver
  • Sahil_Patni's avatar
    Sahil_Patni
    9 months ago

    Hi,

    Yes,  when you enable the TX/RX P&N Invert options in the TSE IP Analog Parameters GUI, you must also perform the Attribute Access Method steps (as described in GTS Attribute Access Method Example 3) after entering user mode.

    This requirement applies because the TSE IP uses the same underlying PMA attributes as the GTS PHY. The GUI setting alone doesn’t apply the inversion until the attribute access sequence is executed.

    Best Regards,

    Sahil Patni

Anonymous's avatar
Anonymous
Not applicable
10 months ago

Hi,

Thank you for your inquiry regarding the GTS TX and RX polarity inversion features.

Starting from Quartus version 25.1.1, these features are supported in hardware. However, please note that after enabling the polarity inversion options in the IP GUI, you must also follow the steps outlined in Example 3 of the GTS Attribute Access Method section in the user guide to complete the configuration.

Regarding your question about the polarity inversion option in Quartus 25.1, since the user guide indicates that it is not supported in hardware, it is likely intended for simulation purposes only.

Please feel free to reach out if you have any further questions or concerns. Thank you.