New ContributorAvalon-MM to PCIe address translation table settings
Trying to DMA from DDR3 memory through PCIe Txs port back to external CPU memory using a mSGDMA engine in a Cyclone V GT device. The mSGDMA is working and I can see the Txs Avalon-MM interface transacting correctly in SignalTap. The data and addresses are correct and the DMA completes normally. But the DMA data never shows up in external CPU memory (at least not where it's supposed to).
We walked through how to set up the address translation registers very carefully and thought we nailed it, but something is wrong and everything points to a PCIe addressing problem. Below is how we set the registers. Hoping that someone can check our work and indicate what, if anything, we screwed up.
The translation settings in the PCIe hard IP core are 2 pages with 16MB per page. There are 25 address bits on the Txs Avalon-MM port.
The 32-bit base address of the Txs port in Platform Designer is 0x8000_0000.
The destination start address in external CPU memory is 0x3DD39B10.
Per the "Cyclone V Avalon-MM Interface for PCIe Solutions User Guide", bits [23:0] of the Txs address pass through to the PCIe address and bit [24] selects between the two pages of the translation table.
We're setting the translation table registers as follows:
0x1000 = 0x3C00_0000
- Bits [31:25] = top 7 bits of target address 0x3DD39B10 = binary 0011110.
- Bit [24] = bit [24] of Txs Avalon-MM address which is 0 in this first page.
- Bits [23:2] = 0 (these address bits pass through to PCIe and are not translated)
- Bits [1:0] = 2'b00 for 32-bit PCIe address
0x1004 = 0 (ignored for 32-bit addressing)
0x1008 = 0x3D00_0000
- Bits [31:25] = top 7 bits of target address 0x3DD39B10 = binary 0011110.
- Bit [24] = bit [24] of Txs Avalon-MM address which is 1 in this second page.
- Bits [23:2] = 0 (these address bits pass through to PCIe and are not translated)
- Bits [1:0] = 2'b00 for 32-bit PCIe address
0x100C = 0 (ignored for 32-bit addressing)
It's possible that there's a software problem in the external CPU, but I want to make 100% sure that the address translation table is correct before I try to blame the software guy.
Thanks in advance for any help provided.
Hi BobSD,
From what you provided compared with the user guide. It is seen to be correct.
But I cannot 100 % confirm that as it is your custom design.
As you are using a single MSGDMA.
What alternative you can do to double confirm is to refer to the design example provided in the previous post.
Set the parameter accordingly and monitor if you are able to get the desired output/result.
Let me know if there is any other things I can help you.
Regards,Wincent_Intel
