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BobSD's avatar
BobSD
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Avalon-MM to PCIe address translation table settings

Trying to DMA from DDR3 memory through PCIe Txs port back to external CPU memory using a mSGDMA engine in a Cyclone V GT device. The mSGDMA is working and I can see the Txs Avalon-MM interface transa...
Pcie
  • Wincent_Altera's avatar
    Wincent_Altera
    2 years ago

    Hi BobSD,

    From what you provided compared with the user guide. It is seen to be correct.
    But I cannot 100 % confirm that as it is your custom design.

    As you are using a single MSGDMA.
    What alternative you can do to double confirm is to refer to the design example provided in the previous post.
    Set the parameter accordingly and monitor if you are able to get the desired output/result.

    Let me know if there is any other things I can help you.

    Regards,

    Wincent_Intel

BobSD's avatar
BobSD
Icon for New Contributor rankNew Contributor
2 years ago

Just one mSGDMA in the design. As I said in my original post, "We walked through how to set up the address translation registers very carefully ...". All I'm asking you to do is check our work as described in the original post above and tell me if we did it correctly or not.

Thanks,

Bob

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi BobSD,

From what you provided compared with the user guide. It is seen to be correct.
But I cannot 100 % confirm that as it is your custom design.

As you are using a single MSGDMA.
What alternative you can do to double confirm is to refer to the design example provided in the previous post.
Set the parameter accordingly and monitor if you are able to get the desired output/result.

Let me know if there is any other things I can help you.

Regards,

Wincent_Intel

  • BobSD's avatar
    BobSD
    Icon for New Contributor rankNew Contributor
    2 years ago

    That’s all I needed, @Wincent_Altera. Thank you for the help!

    Bob