Forum Discussion
New ContributorAvalon-MM to PCIe address translation table settings
Hi BobSD,
From what you provided compared with the user guide. It is seen to be correct.
But I cannot 100 % confirm that as it is your custom design.
As you are using a single MSGDMA.
What alternative you can do to double confirm is to refer to the design example provided in the previous post.
Set the parameter accordingly and monitor if you are able to get the desired output/result.
Let me know if there is any other things I can help you.
Regards,Wincent_Intel
Regular ContributorHi,
Thanks for contacting Intel. I'm assigned to support request.
I'll investigate and get back to you soon. Thanks for your patience.
Meanwhile, we have a design for PCIe-MSGDma cyclone V which have a simular implementation to you
https://www.rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSILTS
Perhaps you can refer to the qsys connection as a reference and try to implement this in your design.
Best regards,
Wincent_Intel
New ContributorThank you for responding. Just to clarify, our PCIe endpoint in Platform Designer works fine. The processor card (Windows based) in the system can see and talk to the Cyclone V card via PCIe and can write and read back registers, etc. It is able to trigger the mSGDMA to DMA from DDR3 to the PCIe Txs port (which I can see in SignalTap), but the data never makes it into the processor card memory (at least not where software expects it to be). There are three possible problems here as I see it:
- The address translation registers in the Cyclone V PCIe endpoint are not being set up correctly, so the data is not going where it's supposed to.
- The wrong address is being written as the destination (write) address in the mSGDMA descriptor. There is some confusion/doubt by the software team about virtual vs physical addresses. They're currently working on resolving that.
- There is something wrong with the PCIe bus or backplane in our system.
My goal with the post here is to address only #1 above. If the translation table setup is wrong then we'll fix it. If it's correct then we'll move on to #2 and #3. I looked at the design you linked above to see if I could find how the address translation table in the Cyclone V endpoint is initialized in that system, but I was not able to find that information.
I look forward to hearing from you.
Bob in SD
- Wincent_Altera
Hi BobSD,
What is the number of Msgdma that you connected with the PCIe HIP ?
Single or multiple ? is it more than 4 ?For the address translation table of tx slave you can refer to
https://cdrdv2-public.intel.com/655090/ug-01110-1_5.pdf under page 95/288there are some clear instructions on how you can configure it.
Let me know if further clarification is needed.
Regards,Wincent_Intel
- BobSD
Just one mSGDMA in the design. As I said in my original post, "We walked through how to set up the address translation registers very carefully ...". All I'm asking you to do is check our work as described in the original post above and tell me if we did it correctly or not.
Thanks,
Bob
- Wincent_Altera
Hi BobSD,
From what you provided compared with the user guide. It is seen to be correct.
But I cannot 100 % confirm that as it is your custom design.
As you are using a single MSGDMA.
What alternative you can do to double confirm is to refer to the design example provided in the previous post.
Set the parameter accordingly and monitor if you are able to get the desired output/result.
Let me know if there is any other things I can help you.
Regards,Wincent_Intel
