Avalon MM FIFO

Question

Hello,I am currently working with a DE10 Standard FPGA Board and a DC2390 Daughter Card. I am capturing the ADC values generated by the daughter card and then using a fifo in the qsys to store these values. The values are being captured on the FPGA and I intend to forward these values to FIFO, which will then be accessed by the HPS. I am trying to understand how to use the control status registers to manipulate the data write in the FIFO. Could you share some document which provides which bits in the registers denote what function?Also, is there a timing diagram for the FIFO that I can follow?Thanks in advance for your time and assistance!

sstrell · Answer

Embedded Peripherals IP User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/software-control.html

greenlantern01 · Answer

Hello,Thank you for your response! I am using an Avalon FIFO Memory in the Qsys and I have turned on Status interface port for input and output and turned off allow backpressure. It is in Dual Clock mode and input and output types are avalonmm write and read respectively.The data is being captured on the FPGA from the DC2390 daughter card connected via HSMC. I want to forward this data from FPGA to FIFO and therefore have exported in the input, input reset, and the in_csr ports. Could you share what the above registers do? I couldn't find much about them.Also, the in_csr_readdata register currently has bits 1 and 3 high (1). What should I interpret from that?

sstrell · Answer

Without knowing what status register you are reading from, there's no way to interpret what you are asking.  They're all documented at the page I linked you to.  If you are talking about the i_status field, as that page says, these bits interpret to almostempty and empty as the chart there explains.

greenlantern01 · Answer

The documentation is confusing to understand.

These are the registers I see when I export the in_csr port from the FIFO:

1) wrclk_control_slave_address[2:0]

2) wrclk_control_slave_read

3) wrclk_control_slave_writedata[31:0]

4) wrclk_control_slave_write

5) wrclk_control_slave_readdata[31:0]

In the documentation, it only mentions status register. Is wrclk_control_slave_readdata the status register? Does it mean that when:
bit 0 (when high) - FULL
bit 1 (when high) - EMPTY
bit 2 (when high) - ALMOST FULL
bit 3 (when high) - ALMOST EMPTY
Bit 4 (when high) - OVERFLOW
bit 5 (when high) - UNDERFLOW

If so, what do the rest of the registers do?

Thank you

sstrell · Answer

You are using the word "registers" incorrectly. Those are signals, not registers, that make up the in_csr Avalon interface for checking the input side of the FIFO (writing data into the FIFO). They control reading and writing the CSR (control and status registers) of the write side of the FIFO.

In the document, table 269 is showing you the entire register map of this interface. So if you do a word (32-bit) read on this interface at the base address you've set for the in_csr interface in Platform Designer, you'll read the 32-bit fill_level register which is described in table 270.

If you do a read on this interface at the base address + 1 (which may be plus 4 if your host interface is using byte addressing which is the default in Platform Designer), you advance to the next 32-bit word which only includes the 6-bit i_status register where each bit is documented in table 271. The upper 26 bits are unused.

This is how basic memory-mapped addressing works and how it is documented everywhere, so if you are not familiar with this, you may want to do a little googling.

You can also look at the Avalon interface spec here: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-memory-mapped-interfaces.html.

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Avalon MM FIFO

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