Forum Discussion
greenlantern01
Occasional Contributor
2 years agoAvalon MM FIFO
Hello, I am currently working with a DE10 Standard FPGA Board and a DC2390 Daughter Card. I am capturing the ADC values generated by the daughter card and then using a fifo in the qsys to store thes...
sstrell
Super Contributor
2 years agoThey're all in the same document. Click around or download the pdf: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/interface-signals-02827.html
And I already said that when you read the readdata signal, depending on the address you access, the particular bit corresponds to the full, empty, etc. flags you mention as described in table 271. There aren't dedicated signals for these flags if that is what you are asking.
And again, the general function of each signal (readdata, writedata, read, write, address, etc.) is governed by the Avalon standard described in the Avalon spec I linked to.