Forum Discussion

Occasional Contributor

1 year ago

Avalon MM FIFO

Hello, I am currently working with a DE10 Standard FPGA Board and a DC2390 Daughter Card. I am capturing the ADC values generated by the daughter card and then using a fifo in the qsys to store thes...

Pcie

sstrell

Super Contributor

1 year ago

Without knowing what status register you are reading from, there's no way to interpret what you are asking. They're all documented at the page I linked you to. If you are talking about the i_status field, as that page says, these bits interpret to almostempty and empty as the chart there explains.

Forum Discussion

Avalon MM FIFO

Recent Discussions

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

Agilex-7 AXI MCDMA for PCIe hang

Can't generate F-Tile Ethernet Hard IP Design Example

Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset

Agilex 7 slew rate reconfiguration