Occasional Contributor
Super ContributorEmbedded Peripherals IP User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/software-control.html
Occasional ContributorHello,
Thank you for your response!
I am using an Avalon FIFO Memory in the Qsys and I have turned on Status interface port for input and output and turned off allow backpressure. It is in Dual Clock mode and input and output types are avalonmm write and read respectively.
The data is being captured on the FPGA from the DC2390 daughter card connected via HSMC. I want to forward this data from FPGA to FIFO and therefore have exported in the input, input reset, and the in_csr ports.
Could you share what the above registers do? I couldn't find much about them.
Also, the in_csr_readdata register currently has bits 1 and 3 high (1). What should I interpret from that?
