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Occasional ContributorArria10 PCIe Hard IP link bring up issue
Hi,
We are trying to bring-up PCIe (Gen1 x1) interface using Arria 10 PCIe Hard IP on Intel's Arria10 Signal Integrity development board.
The design is found to be working in simulation, but on the board, the link doesn't come up. The PCIe LTSSM state is stuck at 0, looks like receiver detection is not happening. The core_clock o/p from the PCIe core looks fine.
We are suspecting PCIe serial link connectivity issue. As per the board document, we could see 10 transceiver channels being connected to the Hard IP. Any idea, which transceiver to be used for Gen1 x1 purpose? Any other pointers to debug this would be of great help.
rgds,
sunil
17 Replies
SengKok_L_IntelRegular Contributor
Hi Sir,
For PCIe hard IP testing, this is suggested to use the A10 FPGA development kit, where there is a PCIe interface for you to connect to the Root Port.
Here is the link:
Regards -SK
SKuma36Hello SK, Thanks for the response. We don’t have the Arria10 FPGA development kit. We have only the Arria10 Signal Integrity development board. This board also supports PCIe interface via the Samtec Bulls eye connector on the board. We are using one external breakout board to finally connect the SMA signals from the Bulls eye connector to the PCIe edge. Could you pl. help us in understanding the transceiver channels used for this PCIe Hard IP block? We would like to know what FPGA pins to be used to connect the PCIe serial interface signals. If you have any document on this, pl. share it with us. Rgds, sunil- SengKok_L_Intel
Hi Sunil,
As per the SI dev kit, the PCIe group are located at block E & F. See Page 42:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_si_dev_kit.pdf
As per the A10 PCIe user guide, the channel 0 of PCIe is starting from channel 4. See figure 21.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf
Therefore, the PCIex1 should be located at:
GXBR_4E_TX_4n
GXBR_4E_RX_4n
Regards -SK
- SKuma36Hi SK, Thanks for the info. Is it possible to change the location of channel 0 of PCIe to some other channel other than channel 4 (Block E) ? I tried using channel 0 (Block F), but Fitter operation resulted in error. Pl. check the attached snapshots. Rgds, sunil
- SengKok_L_Intel
Hi Sunil,
No, this is not possible. The location of hard IP is fixed, and you have to follow.
Regards -SK
- SKuma36Hi SK, Ok got it. Is there any way we can debug this link bring up issue? I could see some PCIe Link Inspector tool for Stratix 10 FPGA. Do we have any such thing for Arria 10 FPGA? Rgds, sunil
- SengKok_L_Intel
Hi Sunil,
I don't aware if there is any for A10. The things that you can do is to capture the signal tap for the LTSSM and see the status, or you can create a simple design by using Native PHY, and then use the Transceiver Tool Kit to analyze the link.
Regards -SK
- SKuma36Hi SK, I tried capturing the PCIe LTSSM state with SignalTap (snapshot attached). The state machine transitions between Detect_quiet (00) and Detect_Active (01) states, doesn’t goes to Polling state. Looks like receiver detection has failed. I tried looping back TX & RX lines, still see the same issue. Also tried probing the internal PIPE signals, but no activity is seen. Pl. suggest if I need to probe any other signals. Rgds, sunil
- SengKok_L_Intel
Hi Sunil,
You may start with some simple design which using Native PHY and TTK to perform some loopback test, and ensure your hardware setup is alright.
Regards -SK
- SKuma36Hi SK, Is it possible to use a soft PCIe IP core instead of Hard IP for Arria10 FPGA? Rgds, sunil
