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SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Arria10 PCIe Hard IP link bring up issue

Hi, We are trying to bring-up PCIe (Gen1 x1) interface using Arria 10 PCIe Hard IP on Intel's Arria10 Signal Integrity development board. The design is found to be working in simulation, but on the...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Sunil,

As per the SI dev kit, the PCIe group are located at block E & F. See Page 42:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_si_dev_kit.pdf

As per the A10 PCIe user guide, the channel 0 of PCIe is starting from channel 4. See figure 21.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

Therefore, the PCIex1 should be located at:

GXBR_4E_TX_4n

GXBR_4E_RX_4n

Regards -SK