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SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Arria10 PCIe Hard IP link bring up issue

Hi, We are trying to bring-up PCIe (Gen1 x1) interface using Arria 10 PCIe Hard IP on Intel's Arria10 Signal Integrity development board. The design is found to be working in simulation, but on the...
SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hello SK, Thanks for the response. We don’t have the Arria10 FPGA development kit. We have only the Arria10 Signal Integrity development board. This board also supports PCIe interface via the Samtec Bulls eye connector on the board. We are using one external breakout board to finally connect the SMA signals from the Bulls eye connector to the PCIe edge. Could you pl. help us in understanding the transceiver channels used for this PCIe Hard IP block? We would like to know what FPGA pins to be used to connect the PCIe serial interface signals. If you have any document on this, pl. share it with us. Rgds, sunil