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SKuma36
Occasional Contributor
Occasional ContributorArria10 PCIe Hard IP link bring up issue
Hi, We are trying to bring-up PCIe (Gen1 x1) interface using Arria 10 PCIe Hard IP on Intel's Arria10 Signal Integrity development board. The design is found to be working in simulation, but on the...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi Sir,
For PCIe hard IP testing, this is suggested to use the A10 FPGA development kit, where there is a PCIe interface for you to connect to the Root Port.
Here is the link:
Regards -SK
