Arria II GX refclk pins

Question

Hi there,

Is there any assignment I need to set when I use the refclk pins as clk inputs? I am using EP2AGX65CU17C6 device. We connected a differential clock input to pin M19 and M20, which is the refclk[0] pin according to the pinout for this device. But the Quartus gives the following fitting error:

Error: Differential I/O input pin ref_clk_left is assigned to a non differential location M19. However, it must be assigned to a differential input location

Why does Quartus II consider the M19 as a non differential pin?

Thanks,

Hua

altera_forum · Answer

You may need to set the clk pins as lvds in the assignment editor. Because the default may be single ended.

altera_forum · Answer

I did set the I/O signal as lvds in pin planner. Is that enough? Are you saying I should set pins M19 and M20 as lvds in the assignment editor?

altera_forum · Answer

Well we are talking about clk pins (not user io). They have to be set as lvds by somebody. Physically you have connected the lvds pair, but it is not clear what you have done in HDL interface itself when declaring the clk. There is some tool inconsistency here. depending on your tool I believe you should try and declare only the positive signal in your entity, you may then get false warning  about the negative pin but ignore it.

altera_forum · Answer

In top level entity I declared the input signal like:

ref_clk_left : in std_logic;

Then in pin planner, as the attached screenshot, I assigned the ref_clk_left signal to pin M19, and set the IO standard as LVDS.

I also tried using chip_pin and altera_attribute to do it, but got the same result.

attribute chip_pin: string; -- Altera specific pin assignment constraint

attribute chip_pin of ref_clk_left : signal is "M19";

attribute altera_attribute: string;

attribute altera_attribute of ref_clk_left : signal is "-name IO_STANDARD LVDS";

What did you mean when you are saying clk pins and user io? are you saying M19 and M20 are clk pins, and ref_clk_left is the user io? If that's the case, how do I set the M19 and M20 pins to be LVDS?

Thanks,

Hua

altera_forum · Answer

Setting the refclk_p in pin planner should be sufficient, as with any other differential clock or user IO pin. I wonder if LVDS is correct for refclk or if it should use PCML standard.

Forum Discussion

Arria II GX refclk pins

9 Replies

Recent Discussions

Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC

Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO