Arria II GX refclk pins

In top level entity I declared the input signal like:

ref_clk_left : in std_logic;

Then in pin planner, as the attached screenshot, I assigned the ref_clk_left signal to pin M19, and set the IO standard as LVDS.

I also tried using chip_pin and altera_attribute to do it, but got the same result.

attribute chip_pin: string; -- Altera specific pin assignment constraint

attribute chip_pin of ref_clk_left : signal is "M19";

attribute altera_attribute: string;

attribute altera_attribute of ref_clk_left : signal is "-name IO_STANDARD LVDS";

What did you mean when you are saying clk pins and user io? are you saying M19 and M20 are clk pins, and ref_clk_left is the user io? If that's the case, how do I set the M19 and M20 pins to be LVDS?

Thanks,

Hua