Arria II GX kit + SDI + VIP , only CVI->CVO, CVO no output

Please check Qsys. To change util_bridge_1,sdi_in_1,sdi_out_1'clock from 100M to 150M,many signals can be looked using SignalTap II Logic.such as,u1_A2gxSDI3G|rx_video_format,rxdata,tx_std,txdata,sdi_in_1|is_clk,is_data,

is_valid,is_ready,sdi_out_1|is_clk,is_data,is_ready,is_valid,..etc. But there are no video output. If there are no Qsys,only using loopback, there are video output.

Thanks.

Please check Qsys.bmp.

CVI Parameters:

Bits per pixel per color plane:10bits

Number of color planes:2

Color plane transmission format:Paraller

Field order:Field 0 first

Sync signals:Embedded in video

Allow corlor planes in sequence input

use vid_std bus

width of vid_std bus: 3 bits

Extract ancillary packets

Interlaced

widh:1920 pixels

Height-frame/field 0:540

Height-field1:540

Pixel FIFO size:4000

use control port

Generate synchronization outputs:Yes

CVO Parameters:

image width/Active pixels: 1920

image height/Active lines:1080

Bits per pixel per color plane: 10

Number of color planes:2

Color plane transmission format:Paraller

Allow output of channels in sequence

Interlaced video

Synces signals:Embedded in video

Active picture line:21

Ancillary packet insertion line:0

Horizontal blanking:280

Verticla blanking:22

Horizontal sync:0

horizontal front porch:0

Horizontal back porch:0

Vertical sync:0

Vertical front porch:0

Vertical back porch:0

F rising edge line:564

F falling edge line:1

Vertical blanking rising edge line:561

Ancillary packet insetion line:0

Vertica balnking:23

Vertical sync:0

verticl front porch:0

Vertical back porch:0

Pixel fifo size :1920

fifo level at which to start ouput:1919

use control port

Accept synchronization ouputs

Runtime configurable video modes:3

width of vid_std bus:3

The screenshot doesn't give any information, since You've not expanded all the modules and connections are not shown. E.g. now it shows that pipeline bridge slave is not connected.

vid_std shows video standard and has nothing to do with the stream itself.

Hi, Socrates,thank you very much for your reply.

I fixed the design in Qsys.The TPG connect to CVO directly, TPG and CVO no control. If no software control,normally it should be have output,is right? But my CVO no output.

TPG parameter is

Maximum image width:1920,Maximum image height:1080, Bits per pixel per color plane:10,

Colorspace:YCbCr,

Output format: 4:2:2

Color plane configuration: Parallel

Interlacing: Progressive output

Pattern: Color bars

The SDI is tested by loopback. It is OK. There are output.

From Qsys CVO only have the follows parameter:

.sdi_out_1_clocked_video_underflow(),

.sdi_out_1_clocked_video_vid_clk(tx_p2_pclk ),

.sdi_out_1_clocked_video_vid_data(sdi_tx_data_sopc),

.sdi_out_1_clocked_video_vid_ln(sdi_tx_ln_sopc),

.sdi_out_1_clocked_video_vid_trs(sdi_tx_trs_sopc)

A2gxSDI3G_ch4 u1_A2gxSDI3G (

//common

.rst_rx ( reset ), //input

.rst_tx ( reset ), //input

.sdi_gxb_powerdown ( 1'b0 ), //input

.gxb4_cal_clk ( gp_clk ), //input

//core config settings

.enable_ln ( enable_ln_p2 ), //input [0:0]

.enable_crc ( 1'b1 ), //input [0:0]

.en_sync_switch ( ), //input

.enable_hd_search ( 1'b1 ), //input

.enable_sd_search ( 1'b1 ), //input

.enable_3g_search ( 1'b1 ), //input

//tx inputs

.tx_pclk ( tx_p2_pclk ), //input - loopback clock

.tx_serial_refclk ( gxb_refclk ), //input - from pcie 148.5 vcxo

//.txdata ( fifo_data_p2 ), //input [19:0]

.txdata ( sdi_tx_data_sopc), //input [19:0]

.tx_trs ( sdi_tx_trs_sopc ), //input [0:0] - not used

.tx_ln ( {sdi_tx_ln_sopc,sdi_tx_ln_sopc} ), //input [21:0] - not used

//.tx_std_select_hd_sdn ( ), //input

//.tx_data_type_a_bn ( 1'b1 ), //input

//.tx_std (pclk_74),

//.tx_trs ( txtrs_p2 ), //input [0:0] - not used txtrs_p0

// .tx_ln ( {11'b0,txln_p2} ), //input [21:0] - not used {11'b0,txln_p0}

.tx_std ( tx_std_p2 ), // tx_std_p0

//tx outputs

.sdi_tx ( hsma_tx_p[0] ), //output [0:0]

.gxb_tx_clkout ( tx_p2_clkout ), //output [0:0]

.tx_status ( tx_p2_stat ), //output [0:0] - not used

//rx inputs

.rx_serial_refclk ( gxb_refclk ), //input

.sdi_rx ( hsma_rx_p[0] ), //input [0:0]

//rx outputs

//.rxdata ( sdi_rx_data), //output [19:0]

//.rx_data_valid_out (sdi_rx_data_valid_out ), //output [1:0]

.rxdata ( rx_p2_data ), //output [19:0]

.rx_data_valid_out ( rx_p2_data_valid ), //output [1:0]

.rx_clk ( rx_p2_clk ), //output -same as "port1_rx_clk"

.rx_status ( rx_p2_status ), //output [10:0]

.rx_ln ( rx_p2_ln ), //output [21:0]

.rx_std ( rx_p2_std ), //output [1:0]

//not used

.rx_anc_data ( rx_p2_anc_d ), //output [19:0]

.rx_anc_valid ( rx_p2_anc_v ), //output [3:0]

.rx_anc_error ( rx_p2_anc_er ), //output [3:0]

.rx_std_flag_hd_sdn ( sdi_rx_std_flag_hd_sdn_0 ), //output [0:0]

.rx_F ( rx_p2_F ), //output [1:0]

.rx_V ( rx_p2_V ), //output [1:0]

.rx_H ( rx_p2_H ), //output [1:0]

.rx_AP ( rx_p2_AP ), //output [1:0]

// reconfig inputs

.sdi_reconfig_clk ( sdi_reconfig_clk ), //input

.sdi_reconfig_togxb ( sdi_reconfig_togxb ), //input [3:0]

.sdi_reconfig_done ( multi_reconfig_done[0] ), //input

//reconfig outputs

.sdi_reconfig_fromgxb ( rc_fromgxb[16:0] ), //output 16 bits

.sdi_start_reconfig ( sdi_start_reconfig[0] ) //output

);

Why is it not output?