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Altera_Forum
Honored Contributor
14 years agoArria II GX kit + SDI + VIP , only CVI->CVO, CVO no output
Arria II GX kit + SDI + VIP , only CVI->CVO, CVO no output. There are is_clk,is_data,vid_clk,vid_data,vid_data_input,no av_readdata,av_writedata,is_active_line_count_f0,is_active_line_count_f1....
Altera_Forum
Honored Contributor
14 years agoPlease check Qsys. To change util_bridge_1,sdi_in_1,sdi_out_1'clock from 100M to 150M,many signals can be looked using SignalTap II Logic.such as,u1_A2gxSDI3G|rx_video_format,rxdata,tx_std,txdata,sdi_in_1|is_clk,is_data,
is_valid,is_ready,sdi_out_1|is_clk,is_data,is_ready,is_valid,..etc. But there are no video output. If there are no Qsys,only using loopback, there are video output. Thanks.