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Altera_Forum
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17 years ago

altmemphy with 2 ram chips

hello all,

Now I'm trying to implement one controller using Altmemphy to interface with two 8-bit DDR2 SDRAM chips on Stratix3.But when I share the address and control signals to both of these devices,i receive these errors:

/*****************************************************/

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[0].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[1].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[2].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[3].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[4].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[5].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[6].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[7].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[8].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[9].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[10].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[11].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.addr[12].addr_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.ba[0].ba_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.ba[1].ba_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.cas_n_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.cke[0].cke_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.cs_n[0].cs_n_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.ras_n_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.we_n_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "stratixIII_3sl150_dev_niosII_standard_sopc:K_S3|CORE_PHY_inst:the_CORE_PHY_inst|CORE_PHY:the_CORE_PHY|MEMPHYDDR2:MEMPHY|MEMPHYDDR2_alt_mem_phy_siii:MEMPHYDDR2_alt_mem_phy_siii_inst|MEMPHYDDR2_alt_mem_phy_addr_cmd_siii:addr_cmd_2t.adc|MEMPHYDDR2_alt_mem_phy_ac_siii:ddr.odt[0].odt_struct|full_rate.addr_pin" has invalid signal-splitter fan-outs.

/*****************************************************/

So please help me to solve that problem or give me an advice to solve that.

Thanks so much,

NPAK

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I guess, the invalid signal-splitter fan-outs means that you connected two physical pins where the IP core expects only one. Altmemphy supports banks of multiple RAM with MEM_IF_CS_WIDTH parameter, but with all ports used as a bus except for the indiviual control signals.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank FvM,

    You guess right,but can you explain more detail about your way to fix this problem?

    Because I want to combine 2 8-bit DDR2SDRAM chips to 16-bit DDR2SDRAM interface so I must share address bus,control signals,... How can i do that without create these error?

    I need your reply as soon as possible.

    Thanks a lot,

    NPAK
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    To my opinion the configuration is identical to a one 16-Bit DDR2-Ram configuration with separate upper and lower DQS and DM pins, as e. g. used with the Cyclone III starter board. In altmemphy configuration, it can be generated by selecting the 8-Bit-Ram preset and setting DQ width to 16 Bit. You can use either one common or two separate clocks, all other pins except for DQx, DQSx and DMx have to be shared by both devices.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hello FvM,

    I also tried doing as you said but if there is any sharing signals,QuartusII still gives me the same error.Do you know how to fix this?(I tried with StratixIII)

    Waiting for your reply,

    Thanks so much,

    NPAK
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Sharing signals, at least for some of the DDR signals, is only possible as connecting both DDR2 RAM pins to a single FPGA pin. Only clock pins can be multiplied. This is the normal situation with RAM modules where 16 and more RAMs are connected to the address and controld lines.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thinking about the discussed invalid signal-splitter fan-outs problem, I wonder why Quartus isn't able to use two ddio_out primitives instead of one, when a user e. g. wants to connect two output pins to an alt_mem_pyh address or control line. Obviously this can't work for inputs or bidirectional pins, but why ddio outputs can't be multiplied?

    In addition, I found that a parameter MEM_ADDR_CMD_BUS_COUNT is trailed through the alt_mem_phy hierarchy, but it isn't evaluated at any place. It seems to be intended for future extensions.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    My Cyclone III dev board was giving me the same kind of problems with Quartus 8.0sp1. I used sopc builder to create a ddr2 controller, but I couldn't split the address and other control lines required to access both "top" and "bot" ram without recieving "has invalid signal-splitter fan-outs.". Sopc builder even has the dev board's exact memory configuration as a preset.

    Happy enough with 128MByte of memory without ecc so I'll just wait til altera get their act together.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I wonder, what has been intended with the hardware design of the Cyclone III 3C120 Development Kit in this point.

    RAM banks with separate control lines (RAS,CAS, addresses) definitely need separate controllers. Or are there any known plans to extend the memory controller IP by a signal-splitter ability?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think that Altera wants us to use these DRams with separate controllers(avoid accessing Dram by many unrelated programs,it makes your system run faster).I also have plan to extend the memory by using 1 controller controls 2 altmemphys.But there is a problem that is how to handle the handshaking process from 2 altmemplhys to my controller.Hope that it is ok.