Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

altmemphy with 2 ram chips

hello all, Now I'm trying to implement one controller using Altmemphy to interface with two 8-bit DDR2 SDRAM chips on Stratix3.But when I share the address and control signals to both of these dev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thinking about the discussed invalid signal-splitter fan-outs problem, I wonder why Quartus isn't able to use two ddio_out primitives instead of one, when a user e. g. wants to connect two output pins to an alt_mem_pyh address or control line. Obviously this can't work for inputs or bidirectional pins, but why ddio outputs can't be multiplied?

In addition, I found that a parameter MEM_ADDR_CMD_BUS_COUNT is trailed through the alt_mem_phy hierarchy, but it isn't evaluated at any place. It seems to be intended for future extensions.