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Altera_Forum
Honored Contributor
Honored Contributoraltmemphy with 2 ram chips
hello all, Now I'm trying to implement one controller using Altmemphy to interface with two 8-bit DDR2 SDRAM chips on Stratix3.But when I share the address and control signals to both of these dev...
Altera_ForumHonored Contributor
Honored ContributorI wonder, what has been intended with the hardware design of the Cyclone III 3C120 Development Kit in this point.
RAM banks with separate control lines (RAS,CAS, addresses) definitely need separate controllers. Or are there any known plans to extend the memory controller IP by a signal-splitter ability?
