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With another project I interface to ADC with the altlvds_rx . The ADC data is buffered in on-chip memory. It works.
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What was the clock-rate inside the FPGA? 200MHz or did you demultiplex it further? How did you write it to on-chip memory?
I assume you had some form of address generator and wrote the data until the RAM was filled.
Think about how you would change that design to turn it into a 'stream'.
The 'stream' from the ADC is a fire hose, it can never be stopped. The RAM is like a bucket. It can only handle a certain amount of data before it is filled. So how do you fill the RAM without it over-flowing? You enable writes to it until it is filled, and then you ignore the ADC data.
So your Avalon system will consist of;
- An ADC that is an Avalon-ST source
- An on-chip SRAM Avalon-ST sink to write the data
- An Avalon-MM register interface for enabling writes to the SRAM (enabling the address generator, and FSM that allows writes to the SRAM).
By using dual-ported RAM, you can write to one side of the on-chip SRAM at the ADC clock frequency and then read from the other side of the SRAM at the Avalon bus frequency.
Lets assume you modify your existing design to get this to work, and then ...
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Just now, I want to store the ADC data on ddr2 sdram. But I don't know how to control the ddr2 with Verilog-HDL and the ddr2 controller in megafunction. So I am trying to implement that with Nios II.
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You don't need the NIOS II processor at all, you can use the JTAG interface (JTAG-to-Avalon-MM master). This interface is used to enable the controller and then poll for done via the registers interface. It never looks at the ADC data (since it is streaming too fast). Once the ADC data is in on-chip RAM or DDR, this interface can read the data from there.
You do need to get the DDR2 controller working. Test it. See how fast you can write data to it. Try using the DMA controllers that Altera provides, or try writing your own. Once you understand how the DDR controller works, you can ...
Modify your ADC design to write to an Avalon-ST sink that is implemented using a FIFO instead of RAM. The ADC data is written to the FIFO at the ADC clock rate, and the data is read from the FIFO at the Avalon bus clock rate. The data gets from the FIFO to the DDR via an Avalon-MM master; either a DMA controller, or one you write that controls the Avalon-MM side of the FIFO.
Ultimately it comes down to how comfortably you are with coding as to how you implement each of the components.
Its a lot to take on if you have not done this before, so start simple. Get each of the pieces working first, eg. for the DDR2 controller, get it working in simulation and then in hardware. Capture SignalTapII traces from the hardware and compare it to the Modelsim simulation waveforms. If you are using a 'slow' master like the NIOS II processor or the JTAG master, the performance will be bad, so add a DMA controller to the design, and DMA from on-chip SRAM to DDR2. This will be your benchmark for determining whether the DDR can handle your ADC data rate.
Have fun!
Cheers,
Dave
Honored Contributor
