--- Quote Start ---
How do you interface to your ADC at the moment? Are you interfacing using LVDS pin constraints and then using DDR registers with a 200MHz clock, or are you using a SERDES (altlvds_rx) component? Either way, you can create an Avalon-ST component that includes that logic. You really need to start moving away from .bsf and learn a hardware description language. It'll make this sort of design significantly easier.
Cheers,
Dave
--- Quote End ---
With another project I interface to ADC with the altlvds_rx . The ADC data is buffered in on-chip memory. It works.
Just now, I want to store the ADC data on ddr2 sdram. But I don't know how to control the ddr2 with Verilog-HDL and the ddr2 controller in megafunction. So I am trying to implement that with Nios II.
Luckily, my program can run on the ddr2 now. And then, I need your help that how to stream the ADC data into the ddr2(I allocate some space on the ddr2 for ADC data).
The ddr2 clk is 150Mhz, the adc data is 8-bits and the ddr2 data width is 16.
How to resolve the ADC data ? Can the Nios II CPU deal with the 400Mbps ADC data ?
Honored Contributor
