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So, you mean that an Avalon-ST component and a SG-DMA will be ok, and I don't need a altlvds_rx block(.bsf) in my top-level .bdf file. Is it all right?
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How do you interface to your ADC at the moment? Are you interfacing using LVDS pin constraints and then using DDR registers with a 200MHz clock, or are you using a SERDES (altlvds_rx) component? Either way, you can create an Avalon-ST component that includes that logic. You really need to start moving away from .bsf and learn a hardware description language. It'll make this sort of design significantly easier.
Cheers,
Dave
Honored Contributor
