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The clock-rate is 400MHz ,generating by a PLL.
I write the ADC data into a fixed depth FIFO , just several thourands of bytes.
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Did you perform a TimeQuest timing analysis to confirm that timing was met at this frequency? If timing was not met, you can demultiplex the data. But make sure you do a timing analysis.
If you configure the altlvds_rx for 1:2 mode, then the PLL will generate a 400MHz clock for capturing data bits, and a 200MHz clock for capturing demultiplexed-by-2 data. This will use the DDR registers in the I/O elements.
If you use higher demultiplexing factors, then the SERDES shift-register will be used. Read some details here for a 1GHz ADC:
http://www.ovro.caltech.edu/~dwh/carma_board/ (
http://www.ovro.caltech.edu/%7edwh/carma_board/)
http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (
http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)
Your new design can still use the FIFO, but once you start writing to it with the ADC, your Avalon-MM master would start reading from it, and then writing the data to the DDR controller.
You first need to determine whether the data rate of the ADC can be matched by the DDR interface. For DDR its not just a simple matter of clock frequencies. You have to determine the average data rate over a large number of bursts that include lost clocks due to refresh and page accesses. Once you know that your DDR can keep up, you can work on creating an Avalon-MM master for the FIFO-to-DDR transfers.
It might seem like the more complicated way to go, however, the DDR controller is best used with an Avalon-MM interface (since that might be your only choice). So, its best to live with what you have and start there.
Cheers,
Dave
Honored Contributor
