altera LVDS receiver

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I am currently debugging LVDS receiver on my hardware implemented by altera IP: altlvds_tx/rx. I am facing a problem. When incoming data include more than 4 or 5 successive 0, the received data would be wrong. My design contains 4 channels. The channel is different from others. Some of channel even has problem when successive 0 is only 4. Some of channels have no problem when successive 0 is 5. I simulated by modelsim, the result is correct. The hardware is a released product which I am sure there is no hardware issue. Can any help me out regarding to this issue? thanks alot.

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Without seeing the schematic and layout, we can only guess ... so here's a few:

1. You have AC coupled your LVDS link, or

2. Your frame clock is misaligned with your LVDS, possibly due to this one channel having a longer trace than the others (though this would have to be a very bad layout to get high enough skew).

3. You are getting coupling between traces, and you just happen to notice it when the other trace has zeros on it. Try toggling one trace and see what is received on all traces.

Cheers,

Dave

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Without seeing the schematic and layout, we can only guess ... so here's a few:

1. You have AC coupled your LVDS link, or

2. Your frame clock is misaligned with your LVDS, possibly due to this one channel having a longer trace than the others (though this would have to be a very bad layout to get high enough skew).

3. You are getting coupling between traces, and you just happen to notice it when the other trace has zeros on it. Try toggling one trace and see what is received on all traces.

Cheers,

Dave

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Thanks Dave for your answers.

The hardware platform I am using is a mature design, which have been using for 3 years in a product. So I assume maybe layout is not a issue. When I try to transmit 0x00 on all channel, all channels would receive wrong data.

Do you know if altlvds_tx/rx support successive 0 transmitting? I read the mannual of the IP and searched for other documents. But there is no mentioning about this.

thanks again for helping me.

Regards

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The hardware platform I am using is a mature design, which have been using for 3 years in a product. So I assume maybe layout is not a issue.

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Ok.

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When I try to transmit 0x00 on all channel, all channels would receive wrong data.

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Have you tried this on multiple versions of the board, just to make sure you are not using a bad one?

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Do you know if altlvds_tx/rx support successive 0 transmitting? I read the mannual of the IP and searched for other documents. But there is no mentioning about this.

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There are no restrictions like this as far as the IP is concerned.

However, the transmitted/received data format does depend on your connection to the 'outside world', eg. if you do AC couple to the fiber receivers, then successive zeros would be bad.

Can you confirm that your hardware connection is LVDS transmitter to LVDS receiver (no AC coupling)?

Cheers,

Dave

Assuming the link is DC coupled, the receiver bit clock may have an unsuitable alignment. I usually determine the timing margins and center the bit clock to the range.

What's your bit rate and expectable sampling window?

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Ok.

Have you tried this on multiple versions of the board, just to make sure you are not using a bad one?

There are no restrictions like this as far as the IP is concerned.

However, the transmitted/received data format does depend on your connection to the 'outside world', eg. if you do AC couple to the fiber receivers, then successive zeros would be bad.

Can you confirm that your hardware connection is LVDS transmitter to LVDS receiver (no AC coupling)?

Cheers,

Dave

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Thanks Dave, it is LVDS link between transmitter and receiver. If there is AC coupling, the bad data may occur for any data rather than only for succesive 0. Is this logic correct? Anyway, I will check if there is AC coupling.

Regards

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Assuming the link is DC coupled, the receiver bit clock may have an unsuitable alignment. I usually determine the timing margins and center the bit clock to the range.

What's your bit rate and expectable sampling window?

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Thanks FvM. Honestly I don't now what the samplng window is and don't know if it is really center alignment. I use Cyconle III device which have limited options to choose.

I use control characters for data alignment as recommended by Altera. I write a component by VHDL dedicated for data alignment. I simualted the design by modelsim, there is no issue. Could you please tell me how to check samping window/center alignment?

Thanks alot

Regards

Sampling window is a term used in the Altera device manuals. It's minimal range for the bitclock edge where the data will be sampled correctly. At 80 MSPS it will be pretty large. But it can't be excluded, that the bitclock is aligned unsuitably by design.

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I use control characters for data alignment as recommended by Altera.

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You didn't tell the involved FPGA family. Are you talking about word alignment or also bit phase alignment (DPA), as available with Arria and Stratix devices?

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Sampling window is a term used in the Altera device manuals. It's minimal range for the bitclock edge where the data will be sampled correctly. At 80 MSPS it will be pretty large. But it can't be excluded, that the bitclock is aligned unsuitably by design.

You didn't tell the involved FPGA family. Are you talking about word alignment or also bit phase alignment (DPA), as available with Arria and Stratix devices?

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The FPGA family is Cyclone III.

Yes, I am talking about word alignment.

Regarding to DPA, this is something I am not sure about. Is this included in the IP? For Cyclone III device family, the DPA settings are not available.

I attached the schematic(bdf). Could you please have a look?

Regards