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Sampling window is a term used in the Altera device manuals. It's minimal range for the bitclock edge where the data will be sampled correctly. At 80 MSPS it will be pretty large. But it can't be excluded, that the bitclock is aligned unsuitably by design.
You didn't tell the involved FPGA family. Are you talking about word alignment or also bit phase alignment (DPA), as available with Arria and Stratix devices?
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The FPGA family is Cyclone III.
Yes, I am talking about word alignment.
Regarding to DPA, this is something I am not sure about. Is this included in the IP? For Cyclone III device family, the DPA settings are not available.
I attached the schematic(bdf). Could you please have a look?
Regards
Honored Contributor
