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Honored Contributoraltera LVDS receiver
I am currently debugging LVDS receiver on my hardware implemented by altera IP: altlvds_tx/rx. I am facing a problem. When incoming data include more than 4 or 5 successive 0, the received data would...
Altera_ForumHonored Contributor
Honored ContributorSampling window is a term used in the Altera device manuals. It's minimal range for the bitclock edge where the data will be sampled correctly. At 80 MSPS it will be pretty large. But it can't be excluded, that the bitclock is aligned unsuitably by design.
--- Quote Start --- I use control characters for data alignment as recommended by Altera. --- Quote End --- You didn't tell the involved FPGA family. Are you talking about word alignment or also bit phase alignment (DPA), as available with Arria and Stratix devices?
